Space-based surveillance systems use infrared detectors coupled to computerized data processors for monitoring heated objects and their movements in the atmosphere below and on the ground. The infrared spectrum covers a wide range of wavelengths, from about 0.75 micrometers to 1 millimeter. The function of infrared detectors is to respond to energy of a wavelength within some particular portion of the infrared region. Heated objects dissipate thermal energy having characteristic wavelengths within the infrared spectrum. Different levels of thermal energy, corresponding to different source temperatures, are characterized by the emission of signals with intensity peaks on different portions of the infrared frequency spectrum. Detectors are selected in accordance with their sensitivity in the range of interest to the designer. Similarly, electronic circuitry that receives and processes the signals from the infrared detectors is also selected in view of the intended detection function.
Current infrared detection systems incorporate arrays of large numbers of discrete, highly sensitive detector elements the outputs of which are connected to sophisticated processing circuity. By rapidly analyzing the pattern and sequence of detector element excitation, the system circuitry can identify and monitor sources of infrared radiation. It is difficult, however, to actually construct structures that mate a million or more detector elements and associated circuitry in a reliable and practical manner. Considerable difficulties are presented in aligning the detector elements with conductors on the connecting module and in isolating adjacent conductors in such a dense environment. Consequently, practical applications for contemporary infrared detection systems have necessitated that further advances be made in areas such as miniaturization of the detector array and accompanying circuity, and improvements in the reliability and economical production of the detector array and accompanying circuitry.
In the prior art, a number of detector array modules have been proposed for coupling an array of closely spaced detectors to processing circuitry. Such modules are typically formed such that all connection to and from the module are disposed on a first horizontal layer, with electronic devices and connecting circuitry disposed within the module on one of several stacked horizontal layers interconnected by vertical conductors, known as vias, extending through the layers. A principal shortcoming of this construction is that a single layer is unduly congested with connections to all detectors and external electronics and must also support a large number of vias extending to the parallel layers. The number of detector elements that may be connected as well as the number of connectors to external electronics that support on-focal plane processors are thereby limited by the size of the connecting layer and the minimum width and spacing of the conductors.
Other modules proposed in the prior art address the congestion and space optimization by orienting the detector array perpendicular to the plane of the module layers, adjacent to one edge of the module. Such constructions are commonly referred to as “Z-technology architectures”. Z-technology modules are typically formed by stacking multiple layers of thin-film substrates and bump bonding an end of each layer to an adjacent row of the detector array. Conductors extending along the surface of the substrates have end portions that are carefully aligned to contact leads from the individual detector elements. Such constructions advantageously avoid wiring congestion associated with connecting all detectors to a single module layer and reduce the accompanying need for vertical vias that detract from the useable space with the module. The detector arrays have pixels which are typically less than a 100 microns apart and are integrated to the modules by flip-chip bump bonding.
To maintain an interconnect directly behind each pixel in the Z direction the module layers must be kept very thin and very close together. The contact leads at the edge faces of the stacked electronics are located upon a conductive layer of approximately 1 micron thickness. A photo-resist pattern to keep the contact leads from bridging to the substrate is not producible to the necessary tolerances. The existing method to connect up contact leads at the edge faces requires that the substrate is etched back so the contact leads protrude from the edge, and an insulating layer is deposited over the edge. The tips of the leads are then lightly lapped to expose the metal contact and delineate a pad around it. Although the existing method has proven generally suitable, it too has producibility problems associated with it. The mechanical lapping parameters are difficult to stabilize and control.
In view of the shortcomings of the existing method, it is desirable to provide a non-mechanical method to delineate precisely located contact pads along the stack edged faces. One way the problem may be addressed is by using a depth-sensitive laser to ablate the coating over the protruding leads. But, that is not a complete remedy as the step of etching back the substrate around the leads is not eliminated.